| 摘要 |
A frame sync detecting circuit and FSK receiver wherein, as shown in the drawing, sequential moving average values (squared marks) are determined, from the over-sample values (solid line) of a received word pattern, in a given symbol interval, and the differences between the sequential moving average values and the respective average values of a given sync word pattern in the given symbol interval are determined as DC offsets ?f. Subsequently, the DC offsets ?f are subtracted from the received word pattern to perform a calculation of correlation with the sync word pattern, thereby determining correlation values designated by black circular dots. Then, if any ones of the correlation values exceed a predetermined threshold value, it is determined that a sync word candidate has been received, so that the symbol values (P11'-P20') of the received word pattern after the DC offset corrections are compared with the symbol values of the sync word pattern. If all of the symbol errors are within a given range, the sync word pattern detection is ultimately determined. |
