发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING SAME |
摘要 |
A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array 122, and a data latch circuit 111 for temporarily latching data captured from the data input/output terminals and writing the data in the memory cell array with a delay in a normal write operation. The device also includes a test mode in which the data latch circuit latches data read to the data input/output terminals in a read operation and writes previously latched data in the memory cell array without newly latching data from the data input/output terminals in a write operation. |
申请公布号 |
US2010027354(A1) |
申请公布日期 |
2010.02.04 |
申请号 |
US20090512573 |
申请日期 |
2009.07.30 |
申请人 |
ELPIDA MEMORY, INC. |
发明人 |
MATSUI YOSHINORI;KANEKO SHOJI |
分类号 |
G11C7/10;G11C7/00;G11C8/18;G11C29/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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