发明名称 Integrated circuit with blocking pin to coordinate entry into test mode
摘要 An integrated circuit (IC) including a blocking pin. An IC may include state logic, a test control unit configured to coordinate access by external circuitry to operating state of the state logic during a test mode, and interface pins configured to couple the integrated circuit to the external circuitry. Shared interface pins may provide input signals to the test control unit during the test mode of operation and may perform distinct I/O functions during normal mode operation. A blocking interface pin, when asserted by external circuitry during normal mode operation, may force test signals derived from at least a portion of the shared interface pins by the test control unit into respective quiescent states, such that subsequent to assertion of the blocking pin, the integrated circuit is operable to enter the test mode of operation from the normal mode of operation without resetting operating state of the state logic.
申请公布号 US7657805(B2) 申请公布日期 2010.02.02
申请号 US20070772328 申请日期 2007.07.02
申请人 SUN MICROSYSTEMS, INC. 发明人 ZIAJA THOMAS ALAN;WOODLING KEVIN D.;MOLYNEAUX ROBERT F.
分类号 G01R31/28 主分类号 G01R31/28
代理机构 代理人
主权项
地址