发明名称 Method and apparatus for reducing latency associated with read operations in a memory system
摘要 Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.
申请公布号 US7657771(B2) 申请公布日期 2010.02.02
申请号 US20070621201 申请日期 2007.01.09
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ALLEN, JR. JAMES J.;JENKINS STEVEN K.;MOSSMAN JAMES A.;TROMBLEY MICHAEL R.
分类号 G06F1/04;G06F13/00 主分类号 G06F1/04
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