发明名称 |
Stratified underfill in an IC package |
摘要 |
A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.
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申请公布号 |
US7656042(B2) |
申请公布日期 |
2010.02.02 |
申请号 |
US20060393050 |
申请日期 |
2006.03.29 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
LII MIRNG-JI;LU SZU WEI;KARTA TJANDRA WINATA;LEE CHIEN-HSIUN |
分类号 |
H01L23/48 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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