| 摘要 |
A semiconductor memory device configured such that the time required for its access test can be reduced comprising a memory cell array, a row decoder, a column decoder, an error correction circuit, and an output circuit. The error correction circuit performs error correction on a code word read through the bit lines selected by the column decoder from ones of memory cells located at places at which the word line selected by the row decoder and the selected bit lines cross over, thereby detecting an error position in the code word to generate error detection data indicating the error position and corrects the information bit in the detected error position to generate error corrected data. The output circuit relays to the outside the error corrected data when a normal operation mode has been designated and the error detection data when a test operation mode has been designated.
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