发明名称 Delay locked loop circuit
摘要 The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off.
申请公布号 US7656223(B2) 申请公布日期 2010.02.02
申请号 US20080193077 申请日期 2008.08.18
申请人 MOSAID TECHNOLOGIES INCORPORATED 发明人 MAI HUY TUONG
分类号 G05F1/10 主分类号 G05F1/10
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