发明名称 Method and apparatus for repeat execution of delay analysis in circuit design
摘要 An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.
申请公布号 US7653889(B2) 申请公布日期 2010.01.26
申请号 US20060524342 申请日期 2006.09.20
申请人 FUJITSU LIMITED 发明人 NITTA IZUMI;SHIBUYA TOSHIYUKI;HOMMA KATSUMI;MATSUOKA HIDETOSHI
分类号 G06F17/50;G06F9/45 主分类号 G06F17/50
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