发明名称 |
Test algorithm selection in memory built-in self test controller |
摘要 |
An integrated circuit chip is provided that comprises on-chip memory and test circuitry. The test circuitry is configured to perform operational testing of the on-chip memory. The test circuitry comprises a controller which is configured to perform a selection out of a plurality of test algorithms to perform the operational testing. The plurality of test algorithms includes a fault detection test algorithm to perform operational testing of the on-chip memory in order to detect whether or not there is a memory fault, without locating the memory fault. The plurality of test algorithms further includes a fault location test algorithm to perform operational testing of the on-chip memory in order to detect and locate a memory fault. Further, a method to perform a memory built-in self test and an MBIST (Memory Built-In Self Test) control circuit template are provided.
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申请公布号 |
US7653845(B2) |
申请公布日期 |
2010.01.26 |
申请号 |
US20060484157 |
申请日期 |
2006.07.11 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
HESSE SIEGFRIED KAY;SEURING MARKUS;HERRMANN THOMAS |
分类号 |
G11C29/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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