发明名称 Multi-level non-volatile memory cell with high-VT enhanced BTBT device
摘要 The present disclosure provides a Non-Volatile Memory (NVM) cell and programming method thereof. The cell can denote at least two logic levels. The cell has a read-transistor with a floating gate, and Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased with a first gate bias voltage such that the BTBT device is in accumulation, to set at least one of the logic levels. A first electrode is coupled to bias the BTBT device with a first bias voltage that is higher than the first threshold voltage. The first bias voltage is controlled such that the BTBT device is in accumulation during a write operation. The injected amount of charge on the floating gate is determined by the first bias voltage.
申请公布号 US7652921(B2) 申请公布日期 2010.01.26
申请号 US20080080127 申请日期 2008.03.31
申请人 VIRAGE LOGIC CORPORATION 发明人 HORCH ANDREW E.;WANG BIN
分类号 G11C16/04 主分类号 G11C16/04
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