| 摘要 |
PURPOSE: A layout of spare logic circuit in semiconductor device is provided to obtain the various spare logic circuit and secure the spanning space of the upper metal layer. CONSTITUTION: The first PMOS(P-channel Metal-Oxide Semiconductor) gate area(131) and the first NMOS(N-channel Metal-Oxide Semiconductor) gate area(231) are arranged on the straight line. The second PMOS gate region(132) and the second NMOS gate region(232) are arranged on the straight line. The sixth PMOS lower metal(156) and sixth NMOS lower metal(256) are expanded. The sixth PMOS lower metal and sixth NMOS lower metal are connected to the respective fifth PMOS lower metal(155) and fifth NPMOS lower metal(255).
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