PURPOSE: A method for forming a semiconductor device is provided to implement high integration by reducing the width of components with a nano scale. CONSTITUTION: A nano structure is formed from a catalyst pattern. The nanostructure is grown on the catalyst pattern. An insulation layer(21) is formed on a substrate(10). The insulation layer surrounds the nano structure. The top of the nano structure is exposed by the planarization of the insulation layer. The opening is formed by removing the nano structure and the catalyst pattern. The opening is defined by the insulation layer. A variable resistance pattern(27) is formed in the opening.
申请公布号
KR20100007200(A)
申请公布日期
2010.01.22
申请号
KR20080067718
申请日期
2008.07.11
申请人
SAMSUNG ELECTRONICS CO., LTD.
发明人
ZHAO JIN SHI;LEE, HAN SIN;BAEK, IN GYU;SIM, HYUN JUN;YIM, EUN KYUNG