发明名称 POWER SEMICONDUCTOR DEVICE
摘要 An impurity concentration profile in a vertical direction of a p type base contact layer of a power semiconductor device has a two-stage configuration. In other word, the impurity concentration profile is highest at an upper face of the p type base contact layer, has a local minimum value at a position other than the upper face and a lower face of the base contact layer, and has a local maximum value at a position lower than the position of the local minimum value.
申请公布号 US2010013010(A1) 申请公布日期 2010.01.21
申请号 US20090502759 申请日期 2009.07.14
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 AKIYAMA MIWAKO;KAWAGUCHI YUSUKE;YAMAGUCHI YOSHIHIRO
分类号 H01L29/78 主分类号 H01L29/78
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