发明名称 TRANSMISSION DEVICE, RECEPTION DEVICE, RATE CONTROL DEVICE, TRANSMISSION METHOD, AND RECEPTION METHOD
摘要 <p>A CPU (14) detects the value of the output bit rate for media data output from a buffer (17), detects the free space of the buffer (17), and calculates the reduction rate by dividing a subtraction value, which is determined by subtracting a reduction rate set value from the detected free space value, by the allocation time. When the input bit rate of the media data that is input to the buffer (17) is lowered in response to the output bit rate value, the CPU (14) adds the detected output rate value and the calculated reduction rate value and lowers the input bit rate value based on the upper limit value of the input bit rate, which is the addition value.</p>
申请公布号 WO2010007749(A1) 申请公布日期 2010.01.21
申请号 WO2009JP03218 申请日期 2009.07.09
申请人 PANASONIC CORPORATION;UKITA, YOSUKE;ANDO, KAZUHIRO;HOSOKAWA, SHUYA 发明人 UKITA, YOSUKE;ANDO, KAZUHIRO;HOSOKAWA, SHUYA
分类号 H04L29/08;H04N7/24;H04N7/26 主分类号 H04L29/08
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