| 摘要 |
<P>PROBLEM TO BE SOLVED: To minimize both of complexity and latency by implementing a hardware of general prime factor algorithm (GPFA) on an integrated circuit. Ž<P>SOLUTION: A device is presented, where the device implements discrete Fourier transform (DFT) in a self-aligned type and in-place format for a composite size that can be factorized into products of mutually prime numbers. In this case, some or all of the numbers can be expressed as a power of a given radix. A DFT device can dynamically change the size of DFT between two consecutive transforms. Also, derivations of the above algorithm are presented to further reduce the latency at the sacrifice of an increase in the complexity. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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