发明名称 ARCHITECTURE FOR VECTOR MEMORY ARRAY TRANSPOSITION USING A BLOCK TRANSPOSITION ACCELERATOR
摘要 A system and method for vector memory array transposition. The system includes a vector memory, a block transposition accelerator, and an address controller. The vector memory stores a vector memory array. The block transposition accelerator reads a vector of a block of data within the vector memory array. The block transposition accelerator also writes a transposition of the vector of the block of data to the vector memory. The address controller determines a vector access order, and the block transposition accelerator accesses the vector of the block of data within the vector memory array according to the vector access order.
申请公布号 US2010017450(A1) 申请公布日期 2010.01.21
申请号 US20090400572 申请日期 2009.03.09
申请人 SUN YANMENG;HU LIANGLIANG 发明人 SUN YANMENG;HU LIANGLIANG
分类号 G06F17/14;G06F17/16 主分类号 G06F17/14
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