| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a multi-phase clock generation circuit which suppresses the increase of current consumption while generating multi-phase clocks with smaller phase differences, and to provide an over-sampling circuit. <P>SOLUTION: The multi-phase clock generation circuit includes: a delay amount control part 11 which includes a pair of input/output terminals, a phase comparator 13 for detecting a phase difference between outputs of two delay lines for generating delays corresponding to a biased voltage at delay control terminals, and an averaging filter 14 for averaging an output of the phase comparator 13 and has a reference voltage connected to one delay control terminal thereof and has an output of the averaging filter 14 connected to the other delay control terminal thereof and performs such control as to give a prescribed phase difference between outputs of respective delay lines; and a clock delay part 20 which includes a plurality of delay lines 21 having the same number of delay elements connected in series, wherein respective delay lines 21 are different by combination of the number of delay elements 22 to which the reference voltage is connected, and the number of delay elements to which the output voltage of the averaging filter 14 is connected. The multi-phase clock generation circuit generates a multi-phase clock with a prescribed phase difference. <P>COPYRIGHT: (C)2010,JPO&INPIT |
