发明名称 SPI-4.2 dynamic implementation without additional phase locked loops
摘要 A method and apparatus for receiving clocked data signals such as SPI-4.2 data signals is described. In one embodiment, each data signal lane is deskewed with respect to the clock by oversampling the signal on that lane, and considering multiple versions of a data sequence at different temporal offsets to the clock for correct reception of a training sequence. One of the temporal offsets is subsequently selected to provide the received bit sequence for that lane. Other embodiments are described and claimed.
申请公布号 US7650525(B1) 申请公布日期 2010.01.19
申请号 US20060538157 申请日期 2006.10.03
申请人 FORCE 10 NETWORKS, INC. 发明人 CHANG PETER;BAINS AMRIK;ASWADHATI AJOY;WANG EDWARD
分类号 G06F1/00 主分类号 G06F1/00
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