| 摘要 |
1,097,449. Data processor. RADIO CORPORATION OF AMERICA. March 31, 1966 [April 16, 1965], No. 14240/66. Heading G4A. A digital electric data processor includes instruction execution registers 12 incorporating an operation code register OP, a plurality of sets of programme execution registers I, II, III, IV providing means for computer operation in any one of a corresponding plurality of different processor states, a processor state control register 30 to enable outputs to, and from, any selected one of the programme execution registers, a decoder coupled to the operation code register to detect privileged or prohibited instructions, gate means 54-57 responsive to the output of the decoder and to a prohibit bit in a register 61-64 in the energized one of the programme execution registers, and means responsive to the output of said gate means to change the contents of the processor state control register. In operation the computer is normally executing the user's instructions and is in state I, the processor state control register 30 and a " 1 out of n " decoder 34 passing an enabling signal on line 361. If, for instance, an " add " instruction occurs in the OP register, the operand address in register AR is used to fetch the operand in memory 6 and place it in a utility register UR. Thereafter the operand is applied to a logic arithmetic unit 15. At the same time the other operand located in a programme execution register in set I is also applied to the logic arithmetic unit. The resulting sum is then applied to a further register in set I in case it is required later in the programme. The sequential execution of the user's programme continues until a switch to another programme occurs. This may be caused by an interrupt such as machine error, request for service of an input-output device, data error &c., or by signals from a control unit 20. The new data is entered in processor state control register 30 which produces an enabling signal on a different line 36. Thus a new programme may be obtained without unloading the data in set 1 of the register into store and loading them with the new programme. The new execution occurs until a switch to a further or the original programme is required. Some instructions can only be executed with the computer in a particular one of its states. These are called privileged instructions and are first decoded by privileged instruction decoder 58 which then enables one, or some or all of the AND gates 54-57. A second input to the gates comes from the one of flip-flops 61-64 which is in the enabled set of registers I-IV. If the computer is in a state such that the new instruction cannot be processed then the AND gate is enabled to cause an interruption and a switch to a new processor state. If the instruction can be processed the AND gate is inhibited. For ease in working one of the registers II-IV3 may be used by more than one set I-IV. For instance (Fig. 3, not shown) register 13 may be connected to the input and output gates of set I and set II to secure transferring the same data from I3 to II3. |
