| 摘要 |
A voltage conversion circuit comprises a first and a second output (O1, O2) which are configured to have an electric load (LD) connected in between, wherein an output signal between the first and a second output (O1, O2) is generated in response to a pulse-width modulated clock signal (PWM). The circuit further comprises a forward branch (FWD) being configured to generate an output voltage (VDC) at the first output (O1) depending on a control signal. A feedback branch (FBK) comprises a comparison circuit (CC) being configured to generate the control signal. The feedback branch (FBK) is configured to provide a first potential corresponding to a voltage (VSINK) at a second output (O2) to a comparison input (CI) of the comparison circuit (CC) during a first sensing period which corresponds to at least a part of a period of a first state of the clock signal (PWM) and to provide a second potential derived from the voltage (VSINK) at a second output (O2) by means of a first charge store (C1) to the comparison input (CI) during a second sensing period which corresponds to a part of a period of a second state of the clock signal (PWM). |
