| 摘要 |
The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having a grid array with interconnection lines located within the useful portions of the edge exclusion zone. This working file is then used by a system, such as a digital lithography system, to form the grid array on the surface of the wafer. The grid array is specific to that wafer. Various aspects of the grid array may also be controlled in the process. For example, the line width, inter-line spacing, and position of the lines comprising the grid array are configurable on a wafer-by-wafer basis.
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