发明名称 LAMINATED SEMICONDUCTOR PACKAGE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a laminated semiconductor package allowing evaluation of output characteristics and confirmation of the connected state of wiring of the package. <P>SOLUTION: The laminated semiconductor package includes a connection pad 103 which is provided on wiring 123 to be series-connected to an SOC chip 101 and to which a ball electrode is connected, wiring connected to the wiring 123, wiring 111 connected to the wiring 123 and an inspection land part 125 connected to the wiring 111. A bonding pad 106, the connection pad 103 and the inspection land part 125 are sequentially series-connected with one another. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010010308(A) 申请公布日期 2010.01.14
申请号 JP20080166462 申请日期 2008.06.25
申请人 RENESAS TECHNOLOGY CORP 发明人 SUZUKI KATSUNORI;MARUYAMA TOSHIYUKI
分类号 H01L25/10;H01L25/11;H01L25/18 主分类号 H01L25/10
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