发明名称
摘要 A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overlying the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole.
申请公布号 JP2010501118(A) 申请公布日期 2010.01.14
申请号 JP20090524709 申请日期 2007.08.16
申请人 发明人
分类号 H01L25/065;H01L25/07;H01L25/18 主分类号 H01L25/065
代理机构 代理人
主权项
地址