| 摘要 |
A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal STp+1 of a p+1'th shift register is situated between the start and end of a start pulse of the output signal STp of a p'th shift register, and one each of a first enable signal through a Q'th enable signal exist in sequence between the start of the start pulse of the output signal STp and the start of the start pulse of the output signal STp+1. The operations of a (p', q)'th NAND circuit are restricted based on period identifying signals, such that the NAND circuit generates scanning signals based only on a portion of the output signal STP corresponding to the first start pulse, the signal obtained by inverting the output signal STp+1, and the q'th enable signal ENq.
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