发明名称 |
Semiconductor Device Layout Having Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors |
摘要 |
A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a substrate portion of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level layout is defined above the substrate portion to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight.
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申请公布号 |
US2010011333(A1) |
申请公布日期 |
2010.01.14 |
申请号 |
US20090563077 |
申请日期 |
2009.09.18 |
申请人 |
TELA INNOVATIONS, INC. |
发明人 |
BECKER SCOTT T.;SMAYLING MICHAEL C. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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地址 |
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