| 摘要 |
Nonvolatile memory devices include a memory cell array including a first memory cell and an adjacent second memory cell and a data input/output circuit configured to operate the first memory cell as an m-bit cell and to operate the second memory cell as an n-bit cell, wherein m is not equal to n. The first and second memory cells may be adjacent cells connected to same word line or to the same bit line. The memory cell array may include a third memory cell adjacent the first memory cell and the data input/output circuit may be further configured to operate the third memory cell as a k-bit cell. The first and second memory cells may be connected to the same word line and the first and third memory cells may be connected to the same bit line. The data input/output circuit may be configured to operate the first memory cell as a j-bit cell responsive to detecting a number of erase operations for the first memory cell meeting a predetermined criterion, wherein j is less than n. In some embodiments, j may be equal to m.
|
