DIGITAL DLL CIRCUIT, AND SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a digital DLL (Delay Locked Loop) circuit reducing jitter of an output signal.

SOLUTION: The digital DLL circuit includes: a phase determination section 1, which selects the number of stages of fixed delay element for delaying a clock signal CLK by one period; and a phase adjustment section 21 which selects the number of stages of fixed delay elements for outputting an input signal IN after delaying it by an optional phase amount on the basis of the number of stages of fixed delay elements selected by the phase determination section 1. The phase adjustment section 21 generates an output signal OUT by delaying the input signal IN by the optional phase amount for a delay time generated by the plurality of stages of fixed delay elements and a variable delay section for adjusting a delay time of each of the fixed delay elements per stage at intervals of 1/2n, on the basis of a selecting signal.

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