| 摘要 |
<P>PROBLEM TO BE SOLVED: To inexpensively reduce jitters without increasing overhead nor extremely degrading MAC efficiency even in a large-scale system provided with a base unit, a plurality of repeaters and a plurality of handsets. <P>SOLUTION: This PLL control device includes a TIM extraction circuit 101, a secondary PLL circuit 102, a time dispersion control circuit 103 and a VCXO 94. The TIM extraction circuit 101 extracts a timing component from an input signal. The secondary PLL circuit 102 outputs 14-bit data controlling the phase and/or frequency of its own clock signal in response to the phase and/or frequency of the extracted timing component. The time dispersion control circuit 103 outputs the 14-bit data output from the secondary PLL circuit 102 by temporally dispersing to 10-bit data by dividing them multiple times. Thereby, the VCXO 94 controls the frequency of an output signal based on the 10-bit data output from the time dispersion control circuit 103. <P>COPYRIGHT: (C)2010,JPO&INPIT |
