Hardware architecture to compute different sizes of DFT

摘要

The invention presented in this document deals with the hardware implementation of the General Prime Factor Algorithm (GPFA) on integrated circuits on the purpose of minimizing both the complexity and the latency. It proposes a device to implement discrete Fourier transforms in a self-sorting and in-place manner for composite sizes that can be factorized into the product of mutually prime numbers, where some or all of these numbers can expressed as the power of a given base number. The described DFT device is able to dynamically changing the size of the DFT between two consecutive transforms. Derivations of the proposed algorithm are presented to further reduce the latency at the expense of an increased complexity.