发明名称 |
SIZE AND RETRY PROGRAMMABLE MULTI-SYNCHRONOUS FIFO |
摘要 |
A size and retry programmable multi-synchronous FIFO. In one embodiment, a multi-synchronous FIFO memory generally comprises a selectable number of addressable memory locations for storing information; read control means synchronized by a read clock for controlling pop transactions configured to read from one or more of the selected number of addressable memory locations; write control means synchronized by a write clock asynchronous to the read clock for controlling push transactions to write to one or more of the selected number of addressable memory locations; and selectable transaction retry control means configured to cause read control means to repeat selected pop transactions and/or cause write control means to repeat selected push transactions. In another embodiment a method of retrying a transaction in a multi-synchronous FIFO having a selectable number of addressable memory locations generally comprises the steps of receiving a transaction request; storing the starting address of the transaction register in a start register; executing the transaction; incrementing the starting address in the transaction register after comparing the incremented address to the selected number of addressable memory locations; receiving a retry request; and retrying the transaction.
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申请公布号 |
US2010005250(A1) |
申请公布日期 |
2010.01.07 |
申请号 |
US20080167064 |
申请日期 |
2008.07.02 |
申请人 |
CRADLE TECHNOLOGIES, INC. |
发明人 |
SIMON MOSHE B.;MACHNICKI ERIK P.;LONGLEY MARK |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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