发明名称 REDUCED MEMORY VECTORED DSL
摘要 A reduced-memory vectored DSL system includes methods and apparatus for reducing the bandwidth and memory storage demands on a vectored DSL system in which FEXT data is transmitted and stored. An upstream-end device such as a DSLAM communicates with a plurality of downstream-end devices such as CPE modems. When test signal data, such as training and/or tracking data, is sent to determine FEXT characteristics of the DSL system, error signals are available for all or substantially all of the upstream and/or downstream frequency band DSL tones used in the system. Dividing a frequency band into sub-bands, only a subset of tones in each sub-band is used for deriving FEXT data, such as a FEXT channel response, FEXT channel coefficients and/or FEXT cancellation coefficients. For tones in the sub-band subsets, full-precision FEXT data values can be derived. For other tones, approximations of the FEXT data can be derived. Alternatively, FEXT data can be defined as a base point and associated differential/incremental values that define full-precision and/or approximation FEXT data with fewer bits by utilizing a ? value relative to either a sub-band base point or relative to another tone's value. Memory is reduced in both the transmission of such FEXT data (between upstream and downstream ends of the DSL system) as well as within an upstream-end device such as a DSLAM that performs vectoring using a separate or internal vectoring processing apparatus. Memory also is reduced in the storage of such FEXT data in or off of the DSLAM or other upstream-end device.
申请公布号 WO2010002908(A2) 申请公布日期 2010.01.07
申请号 WO2009US49283 申请日期 2009.06.30
申请人 VECTOR SILICON, INC.;SANDS, NICHOLAS, P.;FISHER, KEVIN, D. 发明人 SANDS, NICHOLAS, P.;FISHER, KEVIN, D.
分类号 H04L29/02 主分类号 H04L29/02
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