| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress a defect in recognizing an inner lead while preventing miswiring. <P>SOLUTION: A process of electrically connecting a plurality of pads formed on a principal plane of a semiconductor chip with wire bonding regions 5aa of a plurality of inner leads 5a disposed in a periphery of the semiconductor chip through wires includes a step in which an image processing means acquires image data 9 of a region including the plurality of inner leads 5a, a step of recognizing positions of the inner leads 5a within a recognition range 9a including the plurality of adjacent inner leads 5a in the image data 9 obtained by the image processing means, and a step of bonding wires to the bonding wire regions 5aa of the inner leads 5a whose positions are recognized. Here, the plurality of inner leads 5a have first regions 5ab disposed adjacent to the wiring bonding regions 5aa, and the first regions 5ab are disposed in such a manner that first regions 5ab that the adjacent inner leads 5a have are alternately different in light reflectivity. <P>COPYRIGHT: (C)2010,JPO&INPIT |
