| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the layout size of a column ADC circuit by reducing the layout size of a latch circuit. Ž<P>SOLUTION: The column ADC circuit is provided corresponding to each column of a pixel array, reads the pixel signal of a row selected by a vertical scanning circuit, and divides the read pixel signal into two blocks, namely high- and low-order blocks, for successive analog-to-digital conversion. Then, the latch circuit 40 in the column ADC circuit is configured to have a storage capacity capable of storing the digital data of a block having a larger number of bits among the high- and low-order blocks. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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