| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a data bus area occupied in the chip size. <P>SOLUTION: The resistance change type memory is equipped with: first and second memory cell arrays MCA1, MCA2 positioned side by side each other in a first direction, wherein a plurality of memory cells are arranged in a matrix state; a first reference cell array RCA1 arranged in a pair with the first memory cell array; a second reference cell array RCA2 arranged in a pair with the second memory cell array; a first sense amplifier SA-1 shared by the first and second memory cell arrays and arranged between the first and second memory cell arrays; a first data bus DB1 for transferring data of a first readout cell MC-1 arranged in the first memory cell array to the first sense amplifier; a second data bus DB2 for transferring data of a first reference cell RC-1 forming a pair with the first readout cell arranged in the first reference cell array to the first sense amplifier. The first and second data busses, by which both sides of the first sense amplifier are arranged extendedly in a second direction, are intersected each other across the first sense amplifier. <P>COPYRIGHT: (C)2010,JPO&INPIT |
