| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock signal generating device capable of setting optimally a non-overlap time, that a discrete-time type circuit requires, and a duty ratio of a clock signal in the case that the clock signal required in the discrete-time type circuit is varied by an external variation factor such as power supply voltage or environmental temperature. SOLUTION: In the clock signal generating device, a clock signal delay calculation section calculates a delay amount of an N-phase clock signal by including a delay detection circuit for monitoring delay characteristics caused by an external variation factor in a variable delay circuit of a clock signal generation circuit, and a clock signal delay control section is configured to vary the delay amount in the variable delay circuit on the basis of delay variation data, stored in a delay variation data section, with the external variation factor as a parameter and the calculated delay amount of the N-phase clock signal. COPYRIGHT: (C)2010,JPO&INPIT |
