发明名称 SEMICONDUCTOR DEVICE, LAYOUT AND WIRING METHOD THEREOF, AND DATA PROCESSING SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide a via multiplexing technique contributing to high-density wiring. SOLUTION: To connect lines L11, L12 of differing wiring layers, a multiple via cell section 20 is used, which has vias 32, 33 for electrically connecting lines 30, 31 bent in an L shape of different wiring layers at both sides with the L-shaped bent portion therebetween. The vias of the multiple via cell section are on a grid line in an X direction and a grid line in a Y direction both of which are defined with a minimum wiring pitch, and all or part of the vias of the first multiple via cell section deviate from an intersection of the grid line in the X direction and the grid line in the Y direction. The vias of the first multiple via cell section are placed on each of the grid line in the X direction and the grid line in the Y direction, corresponding to the L shape, so that there is not much difference between the spatial conditions in the X direction and the spatial conditions in the Y direction viewed from the first multiple via cell section. Thus, the wirability in the X direction becomes equivalent to that in the Y direction. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010003712(A) 申请公布日期 2010.01.07
申请号 JP20070207425 申请日期 2007.08.09
申请人 RENESAS TECHNOLOGY CORP 发明人 TANAKA TERUYA;MIYAZAKI HIROSHI
分类号 H01L21/82;G06F17/50 主分类号 H01L21/82
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