发明名称 TEST CIRCUIT, INTEGRATED CIRCUIT, EXTERNAL TESTER, MEASUREMENT METHOD OF SETUP TIME, CONTROL PROGRAM, AND READABLE STORAGE MEDIUM
摘要 <P>PROBLEM TO BE SOLVED: To accurately implement a timing test of read data from a data source only a small number of times, and reduce an increase in a cost of the timing test. Ž<P>SOLUTION: A test circuit comprises: a supply clock generated from an external clock; a correction clock as the supply clock signal delayed by a delay means 5; a first multiplexer 6 for inputting a read clock from the outside, and selectively outputting it to the data source; and a second multiplexer 7 for inputting the correction clock signal output from the delay means 5 and the read clock, and selectively outputting them to a clock terminal of a flip-flop 4. The first and second multiplexers 6, 7 are controlled by at least one test input signal. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010002239(A) 申请公布日期 2010.01.07
申请号 JP20080159787 申请日期 2008.06.18
申请人 SHARP CORP 发明人 KUBOTA KAZUTOSHI
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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