发明名称 |
DIGITAL PHASE-LOCKED LOOP OPERATING BASED ON FRACTIONAL INPUT AND OUTPUT PHASES |
摘要 |
In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal. |
申请公布号 |
WO2009073580(A3) |
申请公布日期 |
2010.01.07 |
申请号 |
WO2008US85084 |
申请日期 |
2008.11.29 |
申请人 |
QUALCOMM INCORPORATED;BALLANTYNE, GARY JOHN;SUN, BO |
发明人 |
BALLANTYNE, GARY JOHN;SUN, BO |
分类号 |
H03L7/085 |
主分类号 |
H03L7/085 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|