发明名称 METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE
摘要 PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of an semiconductor-on-insulator device by providing the semiconductor-on-insulator device with a body contact. SOLUTION: In one embodiment, the invention provides a semiconductor device that includes: a substrate including a semiconductor layer positioned overlaying an insulating layer, the semiconducting layer including a semiconducting body and isolation regions present around a perimeter of the semiconducting body; a gate structure overlaying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010004006(A) 申请公布日期 2010.01.07
申请号 JP20080259405 申请日期 2008.10.06
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 CHANG LELAND;CHOU ANTHONY I;NARASIMHA SHREESH;SLEIGHT JEFFREY W
分类号 H01L29/786 主分类号 H01L29/786
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