发明名称 ADJUSTABLE READ LATENCY FOR MEMORY DEVICE PAGE-MODE ACCESS
摘要 <p>A read process in a memory device is optimized. Sub-pages of a page of data are read from storage elements by an internal controller of the memory device at a read speed of the internal controller. At a specific time, the controller sets a READY signal to inform an external host to start reading out data from the buffer in a continuous burst, at the associated read speed of the host, which can differ from the controller's read speed, and asynchronous to the internal controller. The READY signal is set so that the host can complete its burst before the buffer runs out of data, while overall read time is minimized. The controller can also be configured for use with hosts having different read speeds. A host may communicate an identifier to the controller for use in determining an optimum time to set the READY signal.</p>
申请公布号 WO2010002753(A1) 申请公布日期 2010.01.07
申请号 WO2009US48991 申请日期 2009.06.29
申请人 SANDISK 3D LLC;LIU, TZ-YI 发明人 LIU, TZ-YI
分类号 G11C7/10 主分类号 G11C7/10
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