| 摘要 |
1370828 Digital transmission; T.D.M. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS CIT-ALCATEL 21 Feb 1972 [19 Feb 1971] 7884/72 Heading H4P A T.D.M. transmitter has a parallel/aerial converter the output being synchronized with clock pulses and a bit added for parity checking. At the receiver the input is decoded and a counter checks the number of data bits received in a cycle, the first items being separated and the remainder are routed to groups of stores identified by the first items. The counter is re-set on reception of an incomplete number. A buffer store MT, when containing data gives a cyclic initiating instruction DC to PO giving in turn an output E1 to bi-stable BB thus initiating clock HL to give periodic pulses, e.g. of 2 Ás to counting element C1 comprising cascaded bistables, which define its state at any step in binary code on outputs A-D and which are presented simultaneously to multiplexers MX1- MXi. Inputs Eo-Em of MX1 &c. receive n data items received from peripheral facilities sent cyclically by a central station of which buffer MT forms part. All multiplexers MX1 &c. present simultaneously to common multiplexer MX outputs corresponding to the instantaneous count in C1. A single data item emitted by MX is dependent on the output F, G by second counting element C2 which extends the range of C1. If the total number of data items is less than the counting capacity of CE an output from parity bi-stable BP1 is inserted into input Ek and transmitted to the receiver, this being a 0 or 1 in dependence of whether the 1 state data items are even or odd. At the receiver R decoder DI separate data from clock signals, the latter being passed through a mono-stable delay B1M and passed to counter CR and input H of register RI each clock pulse received therein enabling it to record a data item from DI. At the third clock pulse, counter CR causes NAND element PE1 to close and thus inhibit further entry of data into RI. |
