发明名称 ISOLATION TECHNIQUE ALLOWING BOTH VERY HIGH AND LOW VOLTAGE CIRCUITS TO BE FABRICATED ON THE SAME CHIP
摘要 An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000 s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.
申请公布号 US2010001365(A1) 申请公布日期 2010.01.07
申请号 US20080165933 申请日期 2008.07.01
申请人 HOPPER PETER J;FRENCH WILLIAM;GABRYS ANN 发明人 HOPPER PETER J.;FRENCH WILLIAM;GABRYS ANN
分类号 H01L29/00;H01L21/762 主分类号 H01L29/00
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