| 摘要 |
A planar extended drain transistor (100) is provided which comprises a control gate (102), a drain region (109), a channel region (107), and a drift region (108), wherein the drift region (108) is arranged between the channel region (107) and the drain region (109). Furthermore, the control gate (102) is at least partially buried into the channel region (107) and the drift region (108) comprises a doping material density which is lower than the doping material density of the drain region (109). |
