发明名称 PROCESSING LONG-LATENCY INSTRUCTIONS IN A PIPELINED PROCESSOR
摘要 There are provided a method and a processor for processing a thread. The thread includes a plurality of sequential instructions. The plurality of sequential instructions include some short-latency instructions and some long-latency instructions and at least one hazard instruction. The hazard instruction requires one or more preceding instructions to be processed before the hazard instruction is processed. The method includes the steps of: a) before processing each long-latency instruction, incrementing by one, a counter associated with the thread; b) after each long-latency instruction has been processed, decrementing by one, the counter associated with the thread; c) before processing each hazard instruction, checking the value of the counter associated with the thread, and i) if the counter value is zero, processing the hazard instruction, or ii) if the counter value is non-zero, pausing processing of the hazard instruction until a later time. The processor includes means for performing steps a), b) and c) of the method.
申请公布号 EP2140347(A1) 申请公布日期 2010.01.06
申请号 EP20080702091 申请日期 2008.02.12
申请人 IMAGINATION TECHNOLOGIES LIMITED 发明人 BERGLAS, Morrie;FOO, Yoong, Chert
分类号 G06F9/38 主分类号 G06F9/38
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