| 摘要 |
PURPOSE: A refresh characteristic test circuit is provided test a refresh characteristic of a memory cell replaced by a redundancy cell by controlling enable of main word line signals. CONSTITUTION: In a device, a test signal generating unit(1) generates a first and the second test signal according to a selection signal and a test mode enable signal. A block signal generating unit(2) generates a plurality of block signals according to a first test signal and at least address signal. A main word line signal generator(3) generates a plurality of main word line signals according to a second test signal and at least second address signal. A sub word line signal generator(4) generates a plurality of sub word line signals according to the test mode enable signal, the second test signal, a plurality of third address signals. A first and the second test signal are enabled selectively in response to the selection signal while the test mode enable signal is activated. |
