| 摘要 |
<p>PURPOSE: A method for forming an overlay vernier of a semiconductor device is provided to reduce an alignment error of a mask pattern in the patterning process of a second layer by using the step height between a first sub-vernier and a first main-vernier. CONSTITUTION: In a device, a first main vernier(101) is formed on a semiconductor substrate(100). The first main vernier has a projecting bar shape. A first sub vernier is formed inside the first main vernier. The first sub vernier has a box type. The second main vernier(102A) is formed by etching a first sub vernier, and the second sub vernier(103) is formed inside the second main vernier. The first main vernier, the second main vernier, and the second sub vernier are formed in the scribe region.</p> |
