发明名称 Method for synchronizing a clock signal with a reference signal, and phase locked loop
摘要 A method for synchronizing a clock signal with a reference signal is disclosed. One embodiment has a first synchronization part which has a bit pattern having a particular clock period, a pause whose length is a multiple of this clock period plus a fraction of the clock period, and a second synchronization part having the particular clock period. The method includes generating a phase difference signal which is proportional to a phase difference between the clock signal and the reference signal, filtering the phase difference signal and providing a filtered phase difference signal, driving a digital oscillator in such a manner that the frequency of the clock signal is changed on the basis of the filtered phase difference signal, the phase of the clock signal within a clock period being corrected by a value corresponding to the fraction of the clock period at an end of the pause in the reference signal.
申请公布号 US7642821(B2) 申请公布日期 2010.01.05
申请号 US20070675191 申请日期 2007.02.15
申请人 INFINEON TECHNOLOGIES AG 发明人 KRASSER GUENTER;DUDA THOMAS
分类号 H03L7/06 主分类号 H03L7/06
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