发明名称 Method for dual damascene process
摘要 The present disclosure provides a method of dual damascene processing. The method includes providing a substrate having vias formed therein; forming an under-layer in the vias and on the substrate; applying a solvent washing process to the under-layer; forming a silicon contained layer on the under-layer; patterning the silicon contained layer (SCL) to form SCL openings exposing the under-layer within the SCL openings; and etching the substrate and the under-layer within the SCL openings to form trenches.
申请公布号 US7642184(B2) 申请公布日期 2010.01.05
申请号 US20070687093 申请日期 2007.03.16
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 CHANG CHING-YU;SHIH JEN-CHIEH
分类号 H01L21/4763 主分类号 H01L21/4763
代理机构 代理人
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