| 摘要 |
A division and square root arithmetic unit carrying out a division operation of a higher radix and a square root extraction operation of a lowe r radix. A certain bit number of data selected from upper bits of the output o f a carry save adder and the output of the adder are input to convert the data into twos complement representation data, and the twos complement representation data is shifted a certain bit number to use the shifted data for a partial remainder of the next digit. Hence, a large number of parts such a s registers of a divisor and a partially extracted square root can be commonly used in a divider and a square root extractor to realize an effective and hi gh performance arithmetic unit. A twos complement converter can be commonly used in the division operation and the square root extraction operation without adding the selector in the return path of the data. Therefore, the lowering of the processing speed in the division operation and the square ro ot extraction operation can be prevented in the division and square root arithmetic unit of the present invention.
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