发明名称 Redundancy structures and methods in a programmable logic device
摘要 An embodiment of the present invention provides a programmable logic device ("PLD") including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.
申请公布号 US7644386(B1) 申请公布日期 2010.01.05
申请号 US20070623903 申请日期 2007.01.17
申请人 发明人 CHAN MICHAEL;LEVENTIS PAUL;LEWIS DAVID;ZAVERI KETAN;YI HYUN MO;LANE CHRIS
分类号 G06F17/50;H03K19/177 主分类号 G06F17/50
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